Bachelor Programmes

Language of Instruction:

English

Learning outcomes:

A student understands the basics of VHDL language and learn to use it in the design of digital circuits like FPGAs and ASICs.

Contents:

An introduction to the HW description languages, basics of VHDL, design description and VHDL tools.

Requirements:

A design exercise and an exam.

Literature:

Informed at the beginning of the course.

Prerequisites:

Digital Circuits and Theory.

Assessment:

Grading scale 0 - 5.

Notes:

Not applicable.

Contact person:

Timo Vainio